A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a solitary processor. It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. A superscalar architecture executes more than one instruction during a single pipeline stage by pre-fetching several instructions and at the same time dispatching them to redundant functional units on the processor.
Seymour Cray's CDC 6600 from 1965 is often mentioned as the first superscalar plan. The Intel i960CA and the AMD 29000-series 29050 microprocessors were the first commercial single-chip superscalar microprocessors. RISC CPUs like these brought the superscalar idea to micro computers because the RISC design results in a simple core, allowing straightforward instruction send off and the inclusion of multiple functional units on a single CPU in the inhibited design rules of the time. This was the reason that RISC designs were faster than CISC designs through the 1980s and into the 1990s.